1. Field of the Invention
The present invention relates to a display driving circuit or displaying a predetermined character on a display panel.
2. Description of the Related Art
FIG. 8 is a block diagram showing a conventional display driving circuit formed integrated on a single chip.
The drawing includes an interface circuit 1 for receiving from an external device (such as a microcomputer) an operation enable signal CE, a clock signal CL, and various data DI for writing.
FIG. 9 shows a specific example of an interface circuit 1. In the drawing, an address register 2 holds address data (e.g., eight bits) in synchronism with a clock signal CL when a chip enable signal CE is at an L level (low level), the address data serving as the key to the operation of the circuit shown in FIG. 8. An address decoder 3 determines whether or not the value of the address register 2 is normal, and outputs "H" (high-level) when the value is determined to be normal. Upon completion of the determination by the address decoder 3, an operation enable signal CE is changed from L to H level. An operation enable signal CE is supplied to one of the input terminals of an AND gate 4, and also to another input terminal thereof via a delay circuit 5 and an inverter 6. That is, when the operation enable signal CE rises from L to H level, the AND gate 4 outputs an H pulse signal. Meanwhile, an operation enable signal CE is also supplied to one of the input terminals of an OR gate 7 and as well as to another input terminal thereof via the delay circuit 5 and the inverter 6. That is, when the operation enable signal CE falls from H to L level, the OR gate 7 outputs an L pulse signal. A D-type flip flop 8 is connected via the D terminal thereof to an output terminal of the address decoder 3, via the C terminal thereof to an output terminal of the AND gate 4, and via the R terminal thereof to an inverted signal of an output from the OR gate 7. Thus, when an operation enable signal CE changes from L to H level, the D-type flip flop 8 holds an H output from the address decoder 3, so that AND gates 9 and 10 are caused to be in an open state. Then, the AND gate 9 outputs various data DI (hereinafter referred to as SDI) for writing into a subsequent memory, and the AND gate 10 outputs a clock signal CL (hereinafter referred to as SCL). An output from the interface circuit 1 is supplied to a shift register (e.g., 24 bits) such that various data SDI is supplied to the shift register in synchronism with a clock signal SCL. When all bits of the various data SDI have been supplied to the shift register, an operation enable signal CE changes from H to L level, and the D-type flip flop 8 is reset. Accordingly, the AND gates 9 and 10 are caused to be in a closed state, thereby suspending shift operation of the shift register.
Referring again to FIG. 8, a shift register 11, corresponding to the above mentioned shift register, serially receives various data SDI for a write of data into the memory (24 bits; D0 to D23) in synchronism with a clock signal SCL during a period when an operation enable signal CE remains at an H level. The shift register 11 is constituted as 24 D-type flip-flops connected in a cascade manner, and employs a serial input and a parallel output format. Note that various data SDI includes address data, display data, an instruction code, and so on.
A character generator ROM 12 stores character data (e.g., 5.times.7 dots (horizontal.times.vertical)) concerning a character to be displayed on a display panel (not shown). Note that the character generator ROM 12 is a non-volatile memory, such as a mask ROM, and is pre-stored, during manufacturing, with character data that is less likely to change. A character generator RAM 13 stores character data concerning other characters to be displayed on the display panel, similar to the character generator ROM 12. Note that the character generator RAM 13 is a volatile memory, such as an SRAM, and stores character data that are very likely to change depending on the situation, under control of an external device. A display RAM 14 stores a character code for designating an address in the character generator ROM 12 or the character generator RAM 13, with an address defined corresponding to each column of a display panel. For example, in the case of a display panel having 64 columns, when the address in the display RAM 14 corresponding to the first column of the display panel is 00H (H: hexadecimal), the address which corresponds to the 64th column is 3FH resulting from incremental addition. An accessory RAM 15 stores accessory data indicative of information other than characters to be displayed on the display panel with an address defined corresponding to each column of a display panel. For example, in the case of 16 types of available accessory information, when the address in the accessory RAM 15 corresponding to the first column of a display panel is OH, the address which corresponds to the 16th column is FH resulting from incremental addition. Note that the accessory RAM 15 is a volatile memory, such as an SRAM, similar to the character generator RAM 13, and the accessory data stored therein can be rewritten as required.
An address counter 16 for use in reading a character code and accessory data supplies address data DCRDA0 to DCRDA5, each being six bits, to the display RAM 14, and address data ADRDA0 to ADRDA3, each being four bits, to the accessory RAM 15.
An instruction decoder 17 generates an instruction signal WCCK for writing character data into the character generator RAM 13, an instruction signal WDCK for writing a character code into the display RAM 14, and an instruction signal WACK for writing accessory data into the accessory RAM 15.
FIG. 10 shows a specific example of an instruction decoder 17. A decoder 18 selectively generates any one of the signals WCENB, WDENB, and WAENB according to the result of decoding the instruction code D20 to D23 supplied from the shift register 11, the signals WCENB, WDENB, and WAENB being used as a base in preparing instruction signals WCCK, WDCK, and WACK. An output DIENB from the D-type flip flop 8 in the interface circuit 1 is supplied to one of the input terminals of a NOR gate 19, and also to another input terminal thereof via a delay circuit 20 and an inverter 21. That is, when a signal DIENB changes from H to L level after completion of shift operation using 24 bits by the shift register 11, the NOR gate 19 outputs an H pulse signal. An output from the NOR gate 19 is supplied to one of the input terminals of each of the AND gates 22, 23, and 24, while the signals WDENB, WAENB, and WCENB from the decoder 18 are supplied to other input terminals of the AND gates 22, 23, and 24, respectively. That is, instruction signals WDCK, WACK, and WCCK are output from the AND gates 22, 23, and 24, respectively, only during a period when an output from the NOR gate 19 remains at an H level.
FIG. 11 shows a specific example of a display RAM 14. A volatile cell array 25 has a read enable terminal OE, a write enable terminal WE, address terminals A0 to A5, and data input/output terminals IO0 to IO7. Switching circuits 26-0 to 26-5 each comprise two AND gates and one OR gate. One of the two AND gates of each of the switching circuits 26-0 to 26-5, i.e., the one shown above in each pair in the drawing, receives via one input terminal thereof corresponding read address data DCRDA0 to DCRDA 5, and receives via another input terminal thereof a switching signal DCRWCT. The AND gate shown below in each pair in the drawing receives via one input terminal thereof corresponding write address data D8 to D13 from the shift register 11, and receives via another input terminal thereof an inverted signal of a switching signal DCRWCT. Latch circuits 27-0 to 27-5 each receive via an L terminal thereof an output from the OR gate of the corresponding switching circuit 26-0 to 26-5, and via a C terminal thereof a clock signal DCLCK, and supply via a Q terminal thereof an output to corresponding address terminal A0 to A5 of the cell array 25. A write enable signal generation circuit 28 generates a write enable signal DCWE at a predetermined timing in response to an instruction signal WDCK supplied from the instruction decoder 17, and supplies the signal DCWE to the write enable terminal WE. A character code D0 to D7 from the shift register 11 is input to the data input/output terminals IO0 to IO7 via buffers 29-0 to 29-7, respectively.
For reading a character code from the display RAM 14, a switching signal DCRWCT becomes H level, upon which address data DCRDA0 to DCRDA5 from the address counter 16 are selectively output from the switching circuits 26-0 to 26-5, and then latched, when a clock signal DCLCK thereafter becomes H level, by the latch circuit 27-0 to 27-5 whereby an address corresponding to the address data DCRDA0 to DCRDA 5 among all addresses in the display RAM 14 is designated. Subsequently, when the read enable signal DCOE becomes H level, a character code consisting of DCDT0 to DCDT 7 is read from the designated address in the display RAM 14. Note that since the buffers 29-0 to 29-7 are in a high impedance state due to the switching signal DCWRDT which is then at an L level, a character code of DCDT0 to DCDT7 when reading does not interfere with a character code D0 to D7 when writing.
For writing a character code into the display RAM 14, a switching signal DCRWCT becomes L level, upon which address data D8 to D13 from the shift register 11 are output from the switching circuits 26-0 to 26-5, and then latched, when a clock signal DCLCK thereafter becomes H level, by the latch circuits 27-0 to 27-5 whereby an address corresponding to the address data D8 to D13 among all addresses in the display RAM 14 is designated. Subsequently, when the write enable signal DCWE becomes H level, a character code D0 to D 7 is written into the designated address in the display RAM 14.
FIG. 12 shows a specific example of an accessory RAM 15. A volatile cell array 30 has a read enable terminal OE, a write enable terminal WE, address terminals A0 to A3, and data input/output terminals IO0 to IO4. Switching circuits 31-0 to 31-3 each comprise two AND gates and one OR gate. One of the two AND gates of each switching circuits 31-0 to 31-3, i.e., the one shown above in the drawing, receives via one input terminal thereof corresponding read address data ADRDA0 to ADRDA 3, and receives via another input terminal thereof an inverted signal of a switching signal ADRWCT. The AND gate shown below in each pair in the drawing receives via one input terminal thereof corresponding write address data D8 to D11 from the shift register 11, and also receives via another input terminal thereof an inverted signal of a switch signal ADRWCT. Latch circuits 32-0 to 32-3 each receive via an L terminal thereof an output from the OR gate of a corresponding switching circuit 31-0 to 31-3, and via a C terminal thereof a clock signal ADLCK, and supply via a Q terminal thereof an output to corresponding address terminal AO to A3 of the cell array 30. A read enable signal ADOE is supplied to the read enable terminal OE. A write enable signal generation circuit 33 generates a write enable signal ADWE at a predetermined timing in response to a supplied instruction signal WACK from the instruction decoder 17, and supplies the signal ADWE to the write enable terminal WE. Accessory data D0 to D4 from the shift register 11 are supplied to corresponding data input/output terminals IO0 to IO4 via buffers 33-0 to 33-4, respectively.
For reading accessory data from the accessory RAM 15, a switching signal ADRWCT becomes H level, upon which address data ADRDA0 to ADRDA3 from the address counter 16 are selectively output from the switching circuits 31-0 to 31-3, and then latched, when a clock signal ADLCK thereafter becomes H level, by the latch circuits 32-0 to 32-3 whereby an address corresponding to the address data of ADRDA0 to ADRDA3 among all addresses in the accessory RAM 15 is designated. Subsequently, when the read enable signal ADOE becomes H level, accessory data of ADDT0 to ADDT4 is read from the designated address in the accessory RAM 15. Note that since the buffers 33-0 to 33-4 are in a high impedance state due to the signal ADWRDT which is then at an L level, accessory data ADDT0 to ADDT4 when reading do not interfere with accessory data D0 to D4 when writing.
For writing accessory data into the accessory RAM 15, a switching signal ADRWCT becomes L level, upon which address data D8 to D11 from the shift register 11 are output from the switching circuits 31-0 to 31-3, and then latched, when a clock signal ADLCK thereafter becomes H level, by the latch circuits 32-0 to 32-3 whereby an address corresponding to the address data D8 to D11 among all addresses in the accessory RAM 15 is designated. Subsequently, when the write enable signal ADWE becomes H level, accessory data D0 to D4 are written into the designated address in the accessory RAM 15.
Note that all 24 bit data held in the shift register 11 is changed prior to writing of a character code and accessory data into the display RAM 14 and the accessory RAM 15, respectively.
Referring again to FIG. 8, a display panel has, for example, 60 segment electrodes and eight common electrodes arranged in a matrix thereon. That is, for a character font consisting of 5.times.7 (horizontal.times.vertical) dots, twelve characters can be displayed on such a display panel as one common electrode is used for displaying accessory information. A latch circuit 34 latches information to be displayed in one horizontal line on the display panel from the character generator ROM 12, the character generator RAM 13, and the accessory RAM 15. A segment driving circuit 35, whose output terminals SEG1 to SEG 60 are connected to the sixty segment electrodes of the display panel, outputs a driving signal for turning on/off light to the segment electrodes. A common driving circuit 36, whose output terminals COMI to COM 8 are connected to the eight common electrodes of the display panel, sequentially outputs a driving signal with a predetermined frequency for activating the segment electrodes. A timing signal generation circuit 37 synchronizes respective blocks of the circuit to ensure reliable displaying of character and accessory information on the display panel.
Here, in order to change character and accessory information which is displayed on a 60.times.80 (horizontal.times.vertical) dot region on the display panel according to generated segment driving signals SEG1 to SEG 60 and common driving signals COM1 to COM8, the content of the display RAM 14 and the accessory RAM 15 must be changed. In other words, the content of the shift register 11 must be changed. Therefore, in order to change the information being displayed on the display panel in each column, address data must be continuously transferred to the shift register 11 even after a character code or accessory data has been written at the write start address in the display RAM 14 or the accessory RAM 15, the address data being obtained through incremental addition to the write start address.
Here, a conventional circuit 1 is such that a write operation with respect to the display RAM 14 and the accessory RAM 15 begins upon completion of shift operation by the shift register 11. In other words, shift operation by the shift register 11 is carried out during a period with an operation enable signal CE remaining H level, and write operation with respect to the display RAM 14 and the accessory RAM 15 is carried out during a period with an operation enable signal CE remaining L level. That is, time for write operation with respect to the display RAM 14 and the accessory RAM 15 is limited, resulting in a problem of inefficient writing. In particular, write processing may be unable to catch up with a significant change, if such occurs, to display information.